This invention relates to decoding wordlines in dynamic random access memory arrays (DRAMs).
Both static random access memory (SRAM) and dynamic random access memory (DRAM) have one or more arrays of memory cells organized into rows (wordlines) and columns (bitlines). Each memory cell represents a single bit and is accessed by a unique address defined by the intersection of a row and a column. In SRAM, each cell is typically directly associated with an input/output pin. In DRAMs, each input/output pin is connected to each memory cell via a xe2x80x9csense amplifierxe2x80x9d, which is usually one or more transistors configured to hold and amplify the charge to be read from or written to the cell. These sense amplifiers take up space and increase capacitance, there by resulting in a xe2x80x9csense amplifier penalty.xe2x80x9d
In order to achieve high speed operations and high memory capacities in DRAMs, memory designers are forced to reduce the row decoding path required to activate a wordline every time a new page of memory is accessed. On the other hand, high-density memory designs require more memory cells per bitline and therefore more sense amplifiers and wordline drivers. The increase in the number of wordline drivers results in increased wordline rise time components attributable to resulting higher diffusion and gate capacitances of the wordline driver control and reset signals. Hence, reading and writing to the wordlines is delayed in the manner of a classic resistance-capacitance (RC) delay.
What is needed is a method and design of decoding wordline drivers so as to overcome such RC delays.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a memory decoder system. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.